It is well known in the art to apply a body bias to the well region of a metal oxide semiconductor field effect transistor (MOSFET) in order to influence the properties of the transistor channel. For example, a forward body bias (FBB) applied to the well influences device operation by decreasing the threshold voltage (Vt) of the transistor. This results in a faster operating device due to increase in the channel current at the expense an increased risk of current leakage. Conversely, a reverse body bias (RBB) applied to the well influences device operation by increasing the threshold voltage (Vt) of the transistor. This results in a device which exhibits a lower current leakage at the expense of a reduced speed. It is accordingly clear that circuit designers can use body bias selection to modulate transistor threshold voltage in effectuating a tradeoff between power and speed for the circuit operation.
There is an increased interest in circuits which operate at ultra-low voltage levels. For example, voltage levels equal to or less than 0.5V for digital circuitry are now becoming common in many applications such as with Internet of Things (IoT) oriented devices. It is common for that digital circuitry to operate in a suspended operating mode (such as sleep or deep-sleep), and when in this mode it is important that the transistors of the digital circuitry have reduced risk of current leakage. To address this concern, the circuit designer may choose to use a reverse body bias (RBB) applied to the well when the sleep (or deep-sleep) operating mode is active. When the digital circuitry is in an active operating mode, switching speed is needed and the circuit designer can choose to use a forward body bias (FBB) applied to the well. Thus, the concept of body bias modulation dependent on mode of digital circuit operation is a well-known strategy to dynamically ensure that the digital circuits can operate a targeted frequency while still supporting a reduction in power consumption.
The additional circuits and logic needed to support the body bias modulation will themselves consume power. In many cases the power reduction of the digital circuitry with body bias modulation dependent on mode of digital circuit operation is more than offset by the power consumption of the additional circuits and logic that are present to support the body bias modulation. The charge pump circuits needed to generate the negative bias voltages for reverse body bias (RBB) or the high bias voltages for forward body bias (FBB) consume large amounts of power and real estate on the chip. For a system on chip (SoC) that is relatively tiny, the area and power impact of the additional circuits and logic is significant. Effort must be made by the circuit designer to minimize the area and power impact.